Data writing method, memory control circuit unit and memory storage device

ABSTRACT

A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold;

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 108114202, filed on Apr. 23, 2019. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND Technical Field

The present invention relates to a data writing method, a memory controlcircuit unit and a memory storage device.

Description of Related Art

The growth of digital cameras, mobile phones, and MP3 players has beenrapid in recent years. Consequently, the consumers' demand for storagemedia has increased tremendously. With characteristics including datanon-volatility, energy saving, small size, lack of mechanicalstructures, high reading/writing speed, etc., rewritable non-volatilememories are most suitable for portable electronic products, such aslaptops. A solid state drive is a memory storage device which utilizes aflash memory as its storage medium. For these reasons, flash memory hasbecome an important part of the electronic industries.

In general, a rewritable non-volatile memory has multiple physicalerasing units, and each physical erasing units has multiple physicalprogramming units. A physical programming unit is usually constituted bymultiple memory cells. The memory management circuit can use a singlepage programming mode or a multi-page programming mode to program (orwrite) data to the physical erasing unit. Here, the programming speed ofprogramming the memory cell based on the single page programming mode ishigher than the programming speed of programming the memory cell basedon the multi-page programming mode (i.e., the time required forprogramming data by using the multi-page programming mode is greaterthan the time required for programming data by using the single pageprogramming mode). Wherein each of the memory cells in the physicalprogramming unit written in the single page programming mode stores onlyone bit of data, and each of the memory cells in the physicalprogramming unit written in the multi-page programming mode storesmultiple bits of data.

In particular, when the memory management circuit performs writeoperations to a physical erasing unit, it is assumed that an abnormalpower-off occurs at this time. After the rewritable non-volatile memorymodule is powered on again., the memory management circuit needs toperform an error recovery mechanism. It is assumed that the memorymanagement circuit uses the multi-page programming mode to write data toa physical erasing unit before power-off. After the rewritablenon-volatile memory module is powered back on, the memory managementcircuit would move (or copy) the valid data in the physical erasing unitthat is being written in the multi-page programming mode before thepower-off to another physical erasing unit. However, moving (or copying)data written in a multi-page programming mode to another physicalerasing unit by using the multi-page programming mode is quite timeconsuming.

In addition, the aforementioned error recovery mechanism can also beaccomplished by a valid data merging operation. For example, it isassumed that the memory management circuit uses the multi-pageprogramming mode to write data to a physical erasing unit beforepower-off. After the rewritable non-volatile memory module is poweredback on, the memory management circuit will determine whether to performthe valid data merging operation (a.k.a. garbage collection operation)at an appropriate timing. For example, when the number of physicalerasing units available for writing in the rewritable non-volatilememory module is insufficient, the memory management circuit can performthe valid data merging operation to move (or copy) the valid data in thephysical erasing unit previously written in the multi-page programmingmode before power-off into another physical erasing unit by using themulti-page programming mode, thereby increasing the number of physicalerasing units available for writing in the rewritable non-volatilememory module and completing the error recovery mechanism performed dueto the power-off. Similarly, moving (or copying) data written inmulti-page programming mode to another physical erasing unit by usingthe multi-page programming mode is quite time consuming.

Therefore, when the rewritable non-volatile memory module is abnormallypowered off, how to quickly perform the error recovery mechanism afterpower-on is one of the problems required to be solved by those skilledin the art.

SUMMARY

The disclosure provides a data writing method, a memory control circuitunit and a memory storage device, which can perform an error recoverymechanism quickly in response to an abnormal power-off of the rewritablenon-volatile memory module after the power is back on.

The disclosure provides a data writing method for a rewritablenon-volatile memory module, wherein the rewritable non-volatile memorymodule comprises a plurality of physical erasing units, each of theplurality of physical erasing units comprises a plurality of physicalprogramming units, the data writing method comprising: receiving a firstwrite command from a host system; determining whether the number of atleast one physical erasing unit available for writing in the pluralityof physical erasing units is greater than a first threshold; when thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is greater than the firstthreshold, selecting a first physical erasing unit from the at least onephysical erasing unit available for writing and writing datacorresponding to the first write command to at least one first physicalprogramming unit of the first physical erasing unit by using a singlepage programming mode or a multi-page programming mode; and when thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is not greater than the firstthreshold, selecting a second physical erasing unit from the at leastone physical erasing unit available for writing and writing the datacorresponding to the first write command to at least one second physicalprogramming unit of the second physical erasing unit by only using thesingle page programming mode.

The disclosure provides a memory control circuit unit for controlling arewritable non-volatile memory module, the memory control circuit unitcomprising: a host interface, a memory interface and a memory managementcircuit. The host interface is configured to couple to the host system.The memory interface is configured to couple to the rewritablenon-volatile memory module, wherein the rewritable non-volatile memorymodule comprises a plurality of physical erasing units, and each of thephysical erasing units comprises a plurality of physical programmingunits. The memory management circuit is coupled to the host interfaceand the memory interface and configured to perform the followingoperations: receiving a first write command from the host system;determining whether the number of at least one physical erasing unitavailable for writing in the plurality of physical erasing units isgreater than a first threshold; when the number of the at least onephysical erasing unit available for writing in the plurality of physicalerasing units is greater than the first threshold, selecting a firstphysical erasing unit from the at least one physical erasing unitavailable for writing and writing data corresponding to the first writecommand to at least one first physical programming unit of the firstphysical erasing unit by using a single page programming mode or amulti-page programming mode; and when the number of the at least onephysical erasing unit available for writing in the plurality of physicalerasing units is not greater than the first threshold, selecting asecond physical erasing unit from the at least one physical erasing unitavailable for writing and writing the data corresponding to the firstwrite command to at least one second physical programming unit of thesecond physical erasing unit by only using the single page programmingmode.

The disclosure provides a memory storage device comprising: a connectioninterface unit, a rewritable non-volatile memory module and a memorycontrol circuit unit. The connection interface unit is configured tocouple to a host system. The rewritable non-volatile memory modulecomprises a plurality of physical erasing units, and each of thephysical erasing units comprises a plurality of physical programmingunits. The memory control circuit unit is coupled to the connectioninterface unit and the rewritable non-volatile memory module andconfigured to perform the following operations: receiving a first writecommand from the host system; determining whether the number of at leastone physical erasing unit available for writing in the plurality ofphysical erasing units is greater than a first threshold; when thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is greater than the firstthreshold, selecting a first physical erasing unit from the at least onephysical erasing unit available for writing and writing datacorresponding to the first write command to at least one first physicalprogramming unit of the first physical erasing unit by using a singlepage programming mode or a multi-page programming mode; and when thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is not greater than the firstthreshold, selecting a second physical erasing unit from the at leastone physical erasing unit available for writing and writing the datacorresponding to the first write command to at least one second physicalprogramming unit of the second physical erasing unit by only using thesingle page programming mode.

Accordingly, the data writing method, the memory control circuit unit,and the memory storage device of the present disclosure can perform theerror recovery mechanism quickly in response to an abnormal power-off ofthe rewritable non-volatile memory module after the power is back on.

To make the aforementioned more comprehensible, several embodimentsaccompanied with drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the disclosure, and are incorporated in and constitutea part of this specification. The drawings illustrate exemplaryembodiments of the disclosure and, together with the description, serveto explain the principles of the disclosure.

FIG. 1 is a schematic diagram illustrating a host system, a memorystorage device and an I/O (input/output) device according to anexemplary embodiment of the invention.

FIG. 2 is a schematic diagram illustrating a host system, a memorystorage device and an I/O device according to another exemplaryembodiment of the invention.

FIG. 3 is a schematic diagram illustrating a host system and a memorystorage device according to another exemplary embodiment of theinvention.

FIG. 4 is a schematic block diagram illustrating a memory storage deviceaccording to an exemplary embodiment of the invention.

FIG. 5A and FIG. 5B are exemplary schematic diagrams illustratingexamples of a memory cell storage structure and a physical erasing unitaccording to an exemplary embodiment of the present invention.

FIG. 6 is a schematic block diagram illustrating a memory controlcircuit unit according to an exemplary embodiment of the invention.

FIG. 7 and FIG. 8 are schematic diagrams illustrating examples ofmanaging the PEUs according to an exemplary embodiment of the presentinvention.

FIG. 9 is a schematic diagram of illustrating examples of writing datainto a RNVM module by using a single page programming mode.

FIG. 10 is a schematic diagram of illustrating examples of writing datainto a RNVM module by using a multi-page programming mode.

FIG. 11 is a schematic diagram of performing a valid data mergingoperation on data written in a single page programming mode by using amulti-page programming mode according to an example.

FIG. 12 is a flow chart of a data writing method according to anexample.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

Embodiments of the present invention may comprise any one or more of thenovel features described herein, including in the Detailed Description,and/or shown in the drawings. As used herein, “at least one”, “one ormore”, and “and/or” are open-ended expressions that are both conjunctiveand disjunctive in operation. For example, each of the expressions “atleast one of A, B and C”, “at least one of A, B, or C”, “one or more ofA, B, and C”, “one or more of A, B, or C” and “A, B, and/or C” means Aalone, B alone, C alone, A and B together, A and C together, B and Ctogether, or A, B and C together.

It is to be noted that the term “a” or “an” entity refers to one or moreof that entity. As such, the terms “a” (or “an”), “one or more” and “atleast one” can be used interchangeably herein.

In general, a memory storage device (a.k.a. a memory storage system)includes a rewritable non-volatile memory module and a controller(a.k.a. a control circuit). The memory storage device usually operatestogether with a host system so the host system can write data into thememory storage device or read data from the memory storage device.

FIG. 1 is a schematic diagram illustrating a host system, a memorystorage device and an I/O (input/output) device according to anexemplary embodiment of the invention. FIG. 2 is a schematic diagramillustrating a host system, a memory storage device and an I/O deviceaccording to another exemplary embodiment of the invention.

Referring to FIG. 1 and FIG. 2, a host system 11 generally includes aprocessor 111, a RAM (random access memory) 112, a ROM (read onlymemory) 113 and a data transmission interface 114. The processor 111,the RAM 112, the ROM 113 and the data transmission interface 114 arecoupled to a system bus 110.

In this exemplary embodiment, the host system 11 is coupled to a memorystorage device 10 through the data transmission interface 114. Forexample, the host system 11 can store data into the memory storagedevice 10 or read data from the memory storage device 10 through thedata transmission interface 114. Further, the host system 11 is coupledto an I/O device 12 via the system bus 110. For example, the host system11 can transmit output signals to the I/O device 12 or receive inputsignals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the RAM 112, theROM 113 and the data transmission interface 114 may be disposed on amain board 20 of the host system 11. The number of the data transmissioninterface 114 may be one or more. Through the data transmissioninterface 114, the main board 20 may be coupled to the memory storagedevice 10 in a wired manner or a wireless manner. The memory storagedevice 10 may be, for example, a flash drive 201, a memory card 202, aSSD (Solid State Drive) 203 or a wireless memory storage device 204. Thewireless memory storage device 204 may be, for example, a memory storagedevice based on various wireless communication technologies, such as aNFC (Near Field Communication) memory storage device, a WiFi (WirelessFidelity) memory storage device, a Bluetooth memory storage device, aBLE (Bluetooth low energy) memory storage device (e.g., iBeacon).Further, the main board 20 may also be coupled to various I/O devicesincluding a GPS (Global Positioning System) module 205, a networkinterface card 206, a wireless transmission device 207, a keyboard 208,a monitor 209 and a speaker 210 through the system bus 110. For example,in an exemplary embodiment, the main board 20 can access the wirelessmemory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, aforementioned host system may be any systemcapable of substantially cooperating with the memory storage device forstoring data. Although the host system is illustrated as a computersystem in foregoing exemplary embodiment, nonetheless, FIG. 3 is aschematic diagram illustrating a host system and a memory storage deviceaccording to another exemplary embodiment of the invention. Referring toFIG. 3, in another exemplary embodiment, a host system 31 may also be asystem including a digital camera, a video camera, a communicationdevice, an audio player, a video player or a tablet computer, and amemory storage device 30 may be various non-volatile memory storagedevices used by the host system, such as a SD card 32, a CF card 33 oran embedded storage device 34. The embedded storage device 34 includesvarious embedded storage devices capable of directly coupling a memorymodule onto a substrate of the host system, such as an eMMC (embeddedMMC) 341 and/or an eMCP (embedded Multi Chip Package) 342.

FIG. 4 is a schematic block diagram illustrating a memory storage deviceaccording to an exemplary embodiment of the invention.

Referring to FIG. 4, the memory storage device 10 includes a connectioninterface unit 402, a memory control circuit unit 404 and a rewritablenon-volatile memory module 406.

In this embodiment, the connection interface unit 402 is compatible witha SATA (Serial Advanced Technology Attachment) standard. Nevertheless,it should be understood that the invention is not limited in thisregard. The connection interface unit 402 may also be compatible to aPATA (Parallel Advanced Technology Attachment) standard, an IEEE(Institute of Electrical and Electronic Engineers) 1394 standard, a PCIExpress (Peripheral Component Interconnect Express) interface standard,a USB (Universal Serial Bus) standard, a SD (Secure Digital) interfacestandard, a UHS-I (Ultra High Speed-I) interface standard, a UHS-II(Ultra High Speed-II) interface standard, a MS (Memory Stick) interfacestandard, a Multi-Chip Package interface standard, a MMC (Multi MediaCard) interface standard, an eMMC (Embedded Multimedia Card) interfacestandard, a UFS (Universal Flash Storage) interface standard, an eMCP(embedded Multi Chip Package) interface standard, a CF (Compact Flash)interface standard, an IDE (Integrated Device Electronics) interfacestandard or other suitable standards. The connection interface unit 402and the memory control circuit unit 404 may be packaged into one chip,or the connection interface unit 402 is distributed outside of a chipcontaining the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a pluralityof logic gates or control commands which are implemented in a hardwarefrom or in a firmware from and perform operations of writing, reading orerasing data in the rewritable non-volatile memory module 406 accordingto the commands of the host system 11.

The rewritable non-volatile memory module 406 is coupled to the memorycontrol circuit unit 404 and configured to store data written from thehost system 11. The rewritable non-volatile memory module 406 hasphysical erasing units 510(0) to 510(N). For instance, the physicalerasing units 510(0) to 510(N) may belong to the same memory die orbelong to different memory dies. Each physical erasing unit has aplurality of physical programming units. For example, in the presentexemplary embodiment, each physical erasing unit contains 258 physicalprogramming units, and physical programming units belonging to the samephysical erasing unit may be written independently and erasedsimultaneously. However, it is to be understood that the presentinvention is not limited thereto, and each physical erasing unit maycontain 64 physical programming units, 256 physical programming units orany number of physical programming units.

To be more detailed, a physical erasing unit is the smallest is thesmallest unit for erasing data, namely, each physical erasing unitcontains the least number of memory cells that are erased all together.A physical programming unit is the smallest unit for programming data,namely, each physical programming unit is the smallest unit for writingdata. Each physical programming unit commonly includes a data bit areaand a redundant bit area, and the data bit area includes a plurality ofphysical access addresses for storing data of users, and the redundantbit area is configured for storing system data (e.g., controlinformation and error correcting codes). In the present exemplaryembodiment, each data bit area of the physical programming unitscontains 4 physical access addresses, and the size of each physicalaccess address is 512 bytes. However, in other exemplary embodiments,more or less number of the physical access addresses may be contained inthe data bit area, and the amount and the size of the physical accessaddresses are not limited in the present invention.

In the present exemplary embodiment, the rewritable non-volatile memorymodule 406 is a trinary-level cell (TLC) NAND flash memory module (i.e.,a flash memory module capable of storing data of 3 bits in one memorycell). However, the present invention is not limited thereto, and therewritable non-volatile memory module 406 may also be a multi-level cell(MLC) NAND flash memory module (i.e., a flash memory module capable ofstoring data of 2 bits in one memory cell), other flash memory modules,or other memory modules having the same characteristics.

FIG. 5A and FIG. 5B are exemplary schematic diagrams illustratingexamples of a memory cell storage structure and a physical erasing unitaccording to an exemplary embodiment of the present invention. In thepresent exemplary embodiment, an MLC NAND flash memory is illustrated asan example for description.

Referring to FIG. 5A, each memory cell in the rewritable non-volatilememory module 406 is capable of storing two bits of data, and a storagestate of each memory cell can be identified as “11”, “10”, “01”, or“00”. In which, each storage state includes the least significant bit(LSB) and the most significant bit (MSB). For example, in the storagestate, the value of the first bit counted from the left is the LSB, andthe value of the second bit counted from the left is the MSB.Accordingly, the memory cells connected to the same word line mayconstitute two physical programming units, in which the physicalprogramming unit constituted by the LSBs of the memory cells is referredto as a lower physical programming unit, and the physical programmingunit constituted by the MSBs of the memory cells is referred to as anupper physical programming unit.

Referring to FIG. 5B, a physical erasing unit is constituted by aplurality of physical programming unit groups, and each physicalprogramming unit group includes the lower physical programming unit andthe upper physical programming unit constituted by the memory cellsarranged on the same word line. For example, in the physical erasingunit, a 0^(th) physical programming unit belonging to the lower physicalprogramming unit and a 1^(st) physical programming unit belonging to theupper physical programming unit are constituted by the memory cellsarranged on word line WLO, therefore being regarded as one physicalprogramming unit group. Similarly, the 2^(nd) and 3^(rd) physicalprogramming units are constituted by the memory cells arranged on wordline WL1, therefore being regarded as one physical programming unitgroup, and the other physical programming units are grouped to aplurality of physical programming unit groups in the same way.

FIG. 6 is a schematic block diagram illustrating a memory controlcircuit unit according to an exemplary embodiment of the invention.

Referring to FIG. 6, the memory control circuit unit 404 includes amemory management circuit 702, a host interface 704, a memory interface706 and an error check and correction circuit 708.

The memory management circuit 702 is configured to control overalloperations of the memory control circuit unit 404. Specifically, thememory management circuit 702 has a plurality of control commands. Whenthe memory storage device 10 operates, the control commands are executedto perform various operations such as data writing, data reading anddata erasing. Hereinafter, description regarding operations of thememory management circuit 702 or any circuit element in the memorycontrol circuit unit 404 is equivalent to description regardingoperations of the memory control circuit unit 404.

In this exemplary embodiment, the control commands of the memorymanagement circuit 702 are implemented in form of firmware. Forinstance, the memory management circuit 702 has a microprocessor unit(not illustrated) and a ROM (not illustrated), and the control commandsare burned into the ROM. When the memory storage device 10 operates, thecontrol commands are executed by the microprocessor to performoperations of writing, reading or erasing data.

In another exemplary embodiment, the control commands of the memorymanagement circuit 702 may also be stored as program codes in a specificarea (for example, the system area in a memory exclusively used forstoring system data) of the rewritable non-volatile memory module 406.In addition, the memory management circuit 702 has a microprocessor unit(not illustrated), the read only memory (not illustrated) and a randomaccess memory (not illustrated). More particularly, the ROM has a bootcode, which is executed by the microprocessor unit to load the controlcommands stored in the rewritable non-volatile memory module 406 to theRAM of the memory management circuit 702 when the memory control circuitunit 404 is enabled. Then, the control commands are executed by themicroprocessor unit to perform operations, such as writing, reading orerasing data.

Further, in another exemplary embodiment, the control commands of thememory management circuit 702 may also be implemented in form ofhardware. For example, the memory management circuit 702 includes amicroprocessor, a memory cell management circuit, a memory writingcircuit, a memory reading circuit, a memory erasing circuit and a dataprocessing circuit. The memory cell management circuit, the memorywriting circuit, the memory reading circuit, the memory erasing circuitand the data processing circuit are coupled to the microprocessor. Thememory cell management circuit is configured to manage the memory cellsof the rewritable non-volatile memory module 406 or a group thereof. Thememory writing circuit is configured to give a write command sequencefor the rewritable non-volatile memory module 406 in order to write datainto the rewritable non-volatile memory module 406. The memory readingcircuit is configured to give a read command sequence for the rewritablenon-volatile memory module 406 in order to read data from the rewritablenon-volatile memory module 406. The memory erasing circuit is configuredto give an erase command sequence for the rewritable non-volatile memorymodule 406 in order to erase data from the rewritable non-volatilememory module 406. The data processing circuit is configured to processboth the data to be written into the rewritable non-volatile memorymodule 406 and the data read from the rewritable non-volatile memorymodule 406. Each of the write command sequence, the read commandsequence and the erase command sequence may include one or more programcodes or command codes, and instruct the rewritable non-volatile memorymodule 406 to perform the corresponding operations, such as writing,reading and erasing. In an exemplary embodiment, the memory managementcircuit 702 may further give command sequence of other types to therewritable non-volatile memory module 406 for instructing to perform thecorresponding operations.

The host interface 704 is coupled to the memory management circuit 702and configured to receive and identify commands and data sent from thehost system 11. In other words, the commands and data transmitted by thehost system 11 are transmitted to the memory management circuit 702 viathe host interface 704. In this exemplary embodiment, the host interface704 is compatible with the SATA standard. Nevertheless, it should beunderstood that the invention is not limited in this regard. The hostinterface 704 may also compatible with the PATA standard, the IEEE 1394standard, the PCI Express standard, the USB standard, the SD standard,the UHS-I standard, the UHS-II standard, the MS standard, the MMCstandard, the eMMC standard, the UFS standard, the CF standard, the IDEstandard, or other suitable standards for data transmission.

The memory interface 706 is coupled to the memory management circuit 702and configured to access the rewritable non-volatile memory module 406.In other words, data to be written into the rewritable non-volatilememory module 406 is converted into a format acceptable by therewritable non-volatile memory module 406 via the memory interface 706.Specifically, if the memory management circuit 702 intends to access therewritable non-volatile memory module 406, the memory interface 706sends corresponding command sequences. For example, the commandsequences may include the write command sequence as an instruction forwriting data, the read command sequence as an instruction for readingdata, the erase command sequence as an instruction for erasing data, andother corresponding command sequences as instructions for performingvarious memory operations (e.g., changing read voltage levels orperforming a garbage collection procedure). These command sequences aregenerated by the memory management circuit 702 and transmitted to therewritable non-volatile memory module 406 through the memory interface706, for example. The command sequences may include one or more signals,or data transmitted in the bus. The signals or the data may includecommand codes and program codes. For example, information such asidentification codes and memory addresses are included in the readcommand sequence.

The error check and correction circuit 708 is coupled to the memorymanagement circuit 702 and configured to perform an error check andcorrection operation to ensure integrity of data. Specifically, when thememory management circuit 702 receives the write command from the hostsystem 11, the error check and correction circuit 708 generates an ECC(error correcting code) and/or an EDC (error detecting code) for datacorresponding to the write command, and the memory management circuit702 writes data and the ECC and/or the EDC corresponding to the writecommand into the rewritable non-volatile memory module 406. Later, whenreading the data from the rewritable non-volatile memory module 406, thememory management circuit 702 will read the corresponding ECC and/or theEDC, and the error check and correction circuit 708 will perform theerror check and correction operation on the read data based on the ECCand/or the EDC.

In an exemplary embodiment, the memory control circuit unit 404 furtherincludes a buffer memory 710 and a power management circuit 712.

The buffer memory 710 is coupled to the memory management circuit 702and configured to temporarily store data and commands from the hostsystem 11 or data from the rewritable non-volatile memory module 406.The power management unit 712 is coupled to the memory managementcircuit 702 and configured to control a power of the memory storagedevice 10.

In this exemplary embodiment, the error check and correction circuit 708can perform a single-frame encoding for the data stored in the samephysical programming unit and can also perform a multi-frame encodingfor data stored in multiple physical programming units. Each of thesingle-frame encoding and the multi-frame encoding may adopt encodingalgorithms including at least one of a LDPC (low density parity code), aBCH code, a convolutional code or a turbo code. Alternatively, inanother exemplary embodiment, the multi-frame encoding may also includea RS codes (Reed-solomon codes) algorithm or an XOR (exclusive OR)algorithm. Further, in another exemplary embodiment, more of otherencoding algorithms not listed above may also be adopted, which areomitted herein. According to the adopted encoding algorithm, the errorcheck and correction circuit 708 can encode the data to be protected, soas to generate the corresponding ECC and/or the EDC.

It is noted that in the following description, some terms may bereplaced with corresponding abbreviations for ease of reading (see Table1).

TABLE 1 rewritable non-volatile memory module RNVM module physicalprogramming unit PPU physical erasing unit PEU memory management circuitMMC

FIG. 7 and FIG. 8 are schematic diagrams illustrating examples ofmanaging the PEUs according to an exemplary embodiment of the presentinvention.

With reference to FIG. 7, the RNVM module 406 has PEUs 510(0) to 510(N),and the MMC 702 logically partitions the PEUs 510(0) to 510(N) into adata area 502, a free area 504, a temporary area 506 and a replacementarea 508.

The PEUs logically belonging to the data area 502 and the free area 504are used for storing data from the host system 11. To be more specific,the PEUs belonging to the data area 502 are regarded as PEUs with datastored therein, and the PEUs belonging to the free area 504 are PEUs inreplacement with the data area 502. Namely, when the host system 11receives a write command and data to be written, the MMC 702 selects aPEU from the free area 504 and writes the data into the selected PEU soas to replace the PEU of the data area 502.

The PEUs logically belonging to the temporary area 506 are used forrecording system data. For instance, the system data includes a logicaladdress-physical address mapping table, the manufacturers and models ofthe RNVM module, the number of physical blocks in the RNVM modules, thenumber of PPUs of each PEU.

The PEUs logically belonging to the replacement area 508 are used forreplacing damaged PEUs. To be more specific, if there are still normalPEUs is the replacement area 508, and a PEU in the data area 502 isdamaged, the MMC 302 elects a normal PEU from the replacement area 508to replace the damaged PEU.

Specially, the number of the PEUs belonging to the data area 502, thefree area 504, the temporary area 506 and the replacement area 508 varywith different memory types. Additionally, it is to be understood thatin the operation of the memory storage device 10, the PEUs associatedwith the data area 502, the free area 504, the temporary area 506 andthe replacement area 508 are dynamically changed. For instance, when onePEU in the free area 504 is damaged and replaced by a PEU of thereplacement area 508, the PEUs originally associated with thereplacement area 508 is associated with the free area 504.

With reference to FIG. 8, the MMC 702 configures logical units LBA(0) toLBA(H) for mapping the PEUs belonging to the data area 502, where eachlogical unit has a plurality of logical sub-units to be mapped to thePPUs of the corresponding PEU. In the meantime, when the host system 11is to write data into a logical unit or update the data stored in thelogical unit, the MMC 702 selects a PEU from the free area 504 forwriting data to alternatively replace the PEU of the data area 502. Inthe present exemplary embodiment, a logical sub-unit may be a logicalpage or a logical sector.

In order to identify where each logical unit of data is stored in thePEU, in the present exemplary embodiment, the MMC 702 records mappingrelations between the logical units and the PEUs. When the host system11 is about to access data in the logical sub-unit, the MMC 702 confirmsthe logical unit where the logical sub-units belong to and accesses datafrom the PEU mapped to the logical unit. For instance, in the presentexemplary embodiment, the MMC 702 stores a logical address-physicaladdress mapping table in the RNVM module 406 for recording each PEUmapped to the logical unit. When accessing data, the MMC 702 loads thelogical address-physical address mapping table o the buffer memory 710for updating.

It should be mentioned that the buffer memory 710 may be incapable ofrecording mapping tables recording the mapping relations of all logicalunits due to its limited capacity. Therefore, in the present exemplaryembodiment, the MMC 702 groups the logical units LBA(0) to LBA(H) into aplurality of logical zones LZ(0) to LZ(M) and assigns one logicaladdress mapping table to each logical zone. Specially, when the MMC 702is going to update the mapping of a logical unit, the logicaladdress-physical address mapping table corresponding to the logical zoneof the logical unit is loaded to the buffer memory buffer memory 710 andis then updated.

In the present embodiment, when the MMC 702 receives a write command(also referred to as a first write command) from the host system 11, theMMC 702 determines whether the number of PEUs (i.e., PEUs available forwriting) in the free area 504 is greater than a first threshold. In thepresent embodiment, the first threshold is, for example, 15. However,the invention is not intended to limit the value of the first threshold.

When the number of PEUs in the free area 504 is greater than the firstthreshold, the MMC 702 issues a first command sequence to select atleast one first PEU from the free area 504, and write data correspondingto the first write command into at least one PPU (also referred to as afirst PPU) of the first PEU by using the single page programming mode orthe multi-page programming mode. It should be noted that, in thisexample, when the number of PEUs in the free area 504 is greater thanthe first threshold, which of the single page programming mode or themulti-page programming mode used by the MMC 702 is determined by thecommands issued by the host system 11. The following examples illustratesingle-page programming mode and multi-page programming mode.

FIG. 9 is a schematic diagram of illustrating examples of writing datainto a RNVM module by using a single page programming mode.

Assuming that the first write command is to instruct storing the datainto the 0th to 255th logical sub-units of the logical unit LBA(0). TheMMC 702 first temporarily stores the data of the first write command tothe buffer memory 710. Then, referring to FIG. 9, the MMC 702 canextract, for example, two PEUs 510(F) and 510 (F+1) from the free area504 as multiple active PEUs corresponding to the first write command.Assuming that the MMC 702 performs write operations by using the singlepage programming mode, the MMC 702 writes the data of the first writecommand from the buffer memory 710 to the PPUs of the PEU 510(F) and thePEU 510 (F+1) according to the first command sequence. That is, it isassumed that the PEUs 510 (F) and 510(F+1) are the aforementioned firstPEU, and the PPUs of the PEUs 510(F) and 510(F+1) are the aforementionedfirst PPU. Here, since the PEU 510(F) and the PEU 510(F+1) areprogrammed by the single page programming mode, as described above, thememory cells constituting the PPUs of the PEU 510(F) and the PEU 510(F+1) are programmed to store 1 bit of data. That is, in the single pageprogramming mode, the lower PPUs of the PEU 510(F) and the PEU 510(F+1)are used to write data and the upper PPUs of the PEU 510(F) and the PEU510(F+1) are not used to write data.

In detail, as shown in FIG. 9, the MMC 702 may sequentially write thedata to be stored into the 0^(th) to 127^(th) logical sub-units of thelogical unit LBA(0) into the lower PPU of the PEU 510(F), andsequentially write the data to be stored into the 128^(th) to 255^(th)logical subunits of the logical unit LBA(0) into the lower PPU of thePEU 510(F+1). That is, the MMC 702 writes the data corresponding to thefirst write command into the lower PPU of the PEU 510(F) and the lowerPPU of the PEU 510(F+1) of the RNVM module 406 from the buffer memory710 by using the single page programming mode, the upper PPU of the PEU510(F) and the upper PPU of the PEU 510(F+1) are not used to write data.

After the operation of writing the data corresponding to the first writecommand into the lower PPU of the PEU 510(F) and the lower PPU of thePEU 510(F+1) of the RNVM module 406 from the buffer memory 710 by usingthe single page programming mode, the MMC 702 may associate the PEU510(F) and the PEU 510(F+1) to the data area 502 and transmit writecompletion information to the host system 11 in response to the firstwrite command issued by the host system 11.

FIG. 10 is a schematic diagram of illustrating examples of writing datainto a RNVM module by using a multi-page programming mode.

Assuming that the first write command is to instruct storing the datainto the 0th to 255th logical sub-units of the logic unit LBA(0), theMMC 702 first temporarily stores the data of the first write command tothe buffer memory 710. Thereafter, referring to FIG. 10, the MMC 702 canextract, for example, one PEU 510 (F+3) from the free area 504 as anactive PEU corresponding to the first write command. Assuming that theMMC 702 performs write operations by using the multi-page programmingmode, the MMC 702 writes the data of the first write command from thebuffer memory 710 to the PPUs of the PEU 510(F+3) according to the firstcommand sequence. That is, it is assumed that the PEU 510(F+3) is theaforementioned first PEU and the PPUs of the PEU 510(F+3) is theaforementioned first PPU. Here, since the PEU 510(F+3) is programmed byusing the multi-page programming mode, as described above, the memorycells constituting the PPUs of the PEU 510(F+3) are programmed to storemultiple bits of data. That is, in the multi-page programming mode, boththe lower PPU and the upper PPU of the PEU 510(F+3) are used to writedata.

In detail, as shown in FIG. 10, the MMC 702 may sequentially write thedata to be stored into the 0^(th) to 255^(th) logical sub-units of thelogical unit LBA(0) into the lower PPU and upper PPU of the PEU510(F+3). That is, the MMC 702 writes the data corresponding to thefirst write command into the lower PPU and the upper PPU of the PEU510(F+3) of the RNVM module 406 from the buffer memory 710 by using themulti-page programming mode.

After the operation of writing the data corresponding to the first writecommand into the lower PPU and the upper PPU of the PEU 510(F+3) of theRNVM module 406 from the buffer memory 710 by using the multi-pageprogramming mode, the MMC 702 may associate the PEU 510(F+3) to the dataarea 502 and transmit write completion information to the host system 11in response to the first write command issued by the host system 11.

In particular, in the present embodiment, when the MMC 702 receives thefirst write command from the host system 11 and the MMC 702 determinesthat the PEU in the free area 504 is not greater than the firstthreshold, the MMC 702 will issue a second command sequence to select atleast one PEU (referred to as a second PEU) from the free area 504, andonly use the single page programming mode to write the datacorresponding to the first write command to at least one PPU (alsoreferred to as a second PPU) of the second PEU without using themulti-page programming mode. How to perform write operations by usingthe single page programming mode has been described in detail as before,and will not be described here.

Thereafter, the MMC 702 determines whether the number of PEUs (i.e.,PEUs available for writing) in the free area 504 is not greater than asecond threshold. In particular, the second threshold is smaller thanthe first threshold.

When the number of PEUs (i.e., PEUs available for writing) in the freearea 504 is not greater than the second threshold, the MMC 702 mayperform a valid data merging operation to copy a plurality of valid datawritten by using the single page programming mode to a plurality of PPUs(also referred to as a third PPU) of another PEU (also referred to as athird PEU) in the free area 504. In other words, by the mechanism thatthe second threshold is less than the first threshold, it can be ensuredthat the MMC 702 performs write operations by using the single pageprogramming mode before performing the valid data merging operation.

The following example illustrates a valid data merging operation.

FIG. 11 is a schematic diagram of performing a valid data mergingoperation on data written in a single page programming mode by using amulti-page programming mode according to an example.

Assuming that the PEU 510(F) and the PEU 510(F+1) of the logical unitLBA(0) has stored valid data of all logical sub-units of the logicalunit LBA(0) (as shown in FIG. 9). When the number of empty PEUs in thefree area 504 is smaller than a preset threshold, the MMC 702 mayperform the valid data merging operation.

In detail, when the number of empty PEUs in the free area 504 is smallerthan a preset threshold, the MMC 702 may perform the valid data mergingoperation. Referring to FIG. 11, when the MMC 702 performs the validdata merging operation, the the MMC 702, for example, selects one PEUfrom the free area 504 as PEU 510(F+2) (hereinafter referred to as thirdPEU) for substitution. Specifically, the MMC 702 selects one blank PEUor one PEU in which the data stored is invalid. Especially, if theselected PEU is the PEU with invalid data, the MMC 702 may first performan erase operation to the PEU. In other words, the invalid data of thePEU should be erased at first.

Afterwards, the MMC 702 copies a plurality of valid data of the PEU510(F) and the PEU 510(F+1) into PPUs of the PEU 510(F+2) of the RNVMmodule 406 by using the multi-page programming mode. Herein, the PEU510(F+2) is programmed by the multi-page programming mode. Accordingly,each memory cell constituting the PPUs of the PEU 510(F+2) is programmedto store multiple bits of data as mentioned above. That is, in themulti-page programming mode, both the lower PPU of the PEU 510(F+2) andthe upper PPU of the PEU 510(F+2) are used to write data.

In detail, the MMC 702 may write (or copy) the valid data belonging tothe 0^(th) to 127^(th) logical sub-units of the logical unit LBA(0) intothe corresponding pages of the PEU 510(F+2) (e.g., the 0^(th) to127^(th) PPUs). After that, the MMC 702 may copy the valid databelonging to the 128^(th) to 255^(th) logical sub-units of the logicalunit LBA(0) into the corresponding pages of the PEU 510(F+2) (e.g., the128^(th) to 255^(th) PPUs). That is, in the multi-page programming mode,the 0^(th) to 255^(th) PPUs (i.e., the third PPU as mentioned above) ofthe PEU 510(F+2) are used to write data.

That is, when performing the valid data merging operation, the PEU to beassociated to the data area 502 is operated by using the multi-pageprogramming mode. Accordingly, PPU groups are taken as units of writingdata into the PEU 510(F+2) simultaneously or periodically. Specifically,in one exemplary embodiment, the 0^(th) and the 1^(st) PPUs of the PEU510(F+2) are programmed simultaneously so as to be written in the dataof the 0^(th) and the 1^(st) logical sub-units of the logical unitLBA(0). The 2^(nd) and the 3^(rd) PPUs of the PEU 510(F+2) areprogrammed simultaneously so as to be written in the data of the 2^(nd)and the 3^(rd) logical sub-units of the logical unit LBA(0). And, it canbe deduced that the data of the other logical subunits are written intothe PEU 510(F+2) in units of the PPU groups.

At last, the MMC 702 may map the logical unit LBA(0) to the PEU510(F+2), perform an erasing operation to the PEUs 510(F)˜510(F+1) andre-associate the PEUs 510(F)˜510(F+1) to the free area 504. That is,when executing the subsequent write commands, the erased PEUs510(F)˜510(F+1) can be again selected as the active PEU of the logicalunit to be written.

By performing the valid data merging operation aforementioned, it can beassured that the available storage capacity of the RNVM module 406 doesnot reduce due to being written by using the single page programmingmode previously.

It should be noted that the foregoing valid data merging operation isdescribed by taking the first PEU written by using the single pageprogramming mode as an example. However, the present invention is notlimited thereto, the foregoing valid data merging operation may be usedalone or in combination in the first PEU and the second PEU written byusing the single page programming mode.

In particular, it is assumed that an abnormal power-off is occurredduring the MMC 702 writing to the RNVM module 406. When the RNVM moduleis powered back on, the MMC 702 needs to perform an error recoverymechanism.

For example, in an embodiment, when the connection interface unit 402(or the host interface 704) receives the first write command from thehost system 11 and the MMC 702 determines that the number of the PEUs inthe free area 504 is not greater than the first threshold, the MMC 702may write the data corresponding to the first write command to thesecond PPU of the second PEU described above by using the single pageprogramming mode. It is assumed that RNVM module 406 occurs an abnormalpower-off during performing the writing operation to the second PPU.After powering back on, the MMC 702 would copy the valid data in thesecond PEU to at least one PPU (also referred to as a fourth PPU) ofanother PEU (also referred to as a fourth PEU) by using the single pageprogramming mode to complete the error recovery mechanism. When the copyoperation is completed, the MMC 702 will reply an information of a readystate to the host system 11. It is worth mentioning that in the presentembodiment, the error recovery mechanism performed by the abnormalpower-off is to move (or copy) the data stored in the single pageprogramming mode to another PEU by using the single page programmingmode, an operation speed of the aforementioned mechanism is faster thanan operation speed of moving (or copying) the data stored in themulti-page programming mode to another PEU by using the multi-pageprogramming mode.

In another embodiment, the error recovery mechanism performed due to thepower-off can also be accomplished through the valid data mergingoperation. In detail, when the connection interface unit 402 (or thehost interface 704) receives the first write command from the hostsystem 11 and the MMC 702 determines that the number of the PEU in thefree area 504 is not greater than the first threshold, the MMC 702 maywrite the data corresponding to the first write command to the secondPPU of the second PEU described above by using the single pageprogramming mode. It is assumed that during the process of writing thesecond PEU, the RNVM module 406 is abnormally powered off. After thepower is turned back on, the MMC 702 will immediately returnedinformation of the ready state to the host system 11. Thereafter, theMMC 702 can determine whether the number of PEUs available for writingin the free area 504 is not greater than the second threshold. When thenumber of PEUs available for writing in the free area 504 is not greaterthan the second threshold, it represents that the number of PEUsavailable for writing in the free area 504 is insufficient. At thistime, the MMC 702 can move (or copy) the data written in the single pageprogramming mode in the second PEU to another PEU by using themulti-page programming mode, and the second PEU is again associated tothe free area 504. Thereby, the number of PEUs available for writing inthe free area 504 can be increased and the error recovery mechanismperformed due to the power-off can be completed.

It is worth mentioning that, in the present embodiment, the valid datamerging operation performed after the abnormal power-off is to move (orcopy) the data stored in the single page programming mode to another PEUby using the multi-page programming mode to obtain a PEU available forwriting, and the execution speed of the aforementioned mechanism isfaster than the speed of a general valid data merging operation thatmoving (or copying) the data stored in the multi-page programming modeto another PEU by using the multi-page programming mode.

It should be noted that the foregoing example is taken the MLC NAND typeflash memory module (i.e., a flash memory module capable of storing 2bits of data in a memory cell) as an example. However, the presentinvention is not limited thereto. In other embodiments, the data writingmethod of the present invention can also be applied to a TLC NAND typeflash memory module, other flash memory module or other memory modulewith the same characteristics.

FIG. 12 is a flow chart of a data writing method according to anexample.

Referring to FIG. 12, in step S1201, the connection interface unit 402(or the host interface 704) receives a first write command from the hostsystem 11. In step S1203, the MMC 702 determines whether the number ofPEUs available for writing is greater than the first threshold. When thenumber of PEUs available for writing is greater than the firstthreshold, in step S1205, the MMC 702 issues a first command sequence toselect a first PEU from the PEUs available for writing and write thedata corresponding to the first write command to the first PPU of thefirst PEU by using the single page programming mode or the multi-pageprogramming mode. In addition, when the number of PEUs available forwriting is not greater than the first threshold, in step S1207, the MMC702 issues a second command sequence to select a second erasing unitfrom the PEU available for writing and write and the data correspondingto the first write command to the second PPU of the second PEU by onlyusing the single page programming mode.

In summary, the data writing method, the memory control circuit unit,and the memory storage device of the present invention can perform theerror recovery mechanism quickly in response to an abnormal power-off ofthe RNVM module after the power is back on.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the disclosed embodimentswithout departing from the scope or spirit of the disclosure. In view ofthe foregoing, it is intended that the disclosure covers modificationsand variations provided that they fall within the scope of the followingclaims and their equivalents.

What is claimed is:
 1. A data writing method for a rewritablenon-volatile memory module, wherein the rewritable non-volatile memorymodule comprises a plurality of physical erasing units, each of theplurality of physical erasing units comprises a plurality of physicalprogramming units, the data writing method comprising: receiving a firstwrite command from a host system; determining whether the number of atleast one physical erasing unit available for writing in the pluralityof physical erasing units is greater than a first threshold; when thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is greater than the firstthreshold, selecting a first physical erasing unit from the at least onephysical erasing unit available for writing and writing datacorresponding to the first write command to at least one first physicalprogramming unit of the first physical erasing unit by using a singlepage programming mode or a multi-page programming mode; and when thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is not greater than the firstthreshold, selecting a second physical erasing unit from the at leastone physical erasing unit available for writing and writing the datacorresponding to the first write command to at least one second physicalprogramming unit of the second physical erasing unit by only using thesingle page programming mode.
 2. The data writing method as claimed inclaim 1, further comprising: determining whether the number of the atleast one physical erasing unit available for writing in the pluralityof physical erasing units is not greater than a second threshold; andwhen the number of the at least one physical erasing unit available forwriting in the plurality of physical erasing units is not greater thanthe second threshold, performing a valid data merging operation, whereinthe second threshold is smaller than the first threshold.
 3. The datawriting method as claimed in claim 2, wherein the step of performing thevalid data merging operation comprises: copying, by using the multi-pageprogramming, a plurality of valid data written in the single pageprogramming mode to a plurality of third physical programming units of athird physical erasing unit of the plurality of physical erasing units.4. The data writing method as claimed in claim 2, further comprising:when the rewritable non-volatile memory module is abnormally powered offand powered back on, performing the step of determining whether thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is not greater than thesecond threshold.
 5. The data writing method as claimed in claim 1,wherein the step of writing the data corresponding to the first writecommand to the at least one second physical programming unit of thesecond physical erasing unit by using the single page programming modecomprises: after the rewritable non-volatile memory module is poweredoff and powered back on, copying a plurality of valid data in the secondphysical erasing unit to at least one fourth physical programming unitof a fourth physical erasing unit of the plurality of physical erasingunits by using the single page programming mode.
 6. The data writingmethod as claimed in claim 1, wherein the first threshold is
 15. 7. Thedata writing method as claimed in claim 1, wherein the first physicalprogramming unit is constituted by a plurality of first memory cells andthe second physical programming unit is constituted by a plurality ofsecond memory cells. in the single page programming mode, each of theplurality of first memory cells constituting the first physicalprogramming unit and each of the plurality of second memory cellsconstituting the second physical programming unit stores only one bit ofdata, and in the multi-page programming mode, each of the plurality offirst memory cells constituting the first physical programming unitstores multiple bits of data.
 8. A memory control circuit unit forcontrolling a rewritable non-volatile memory module, the memory controlcircuit unit comprising: a host interface configured to couple to a hostsystem; a memory interface configured to couple to the rewritablenon-volatile memory module, wherein the rewritable non-volatile memorymodule comprises a plurality of physical erasing units, and each of thephysical erasing units comprises a plurality of physical programmingunits; and a memory management circuit coupled to the host interface andthe memory interface, wherein the memory management circuit isconfigured to receive a first write command from the host system,wherein the memory management circuit is further configured to determinewhether the number of at least one physical erasing unit available forwriting in the plurality of physical erasing units is greater than afirst threshold, when the number of the at least one physical erasingunit available for writing in the plurality of physical erasing units isgreater than the first threshold, the memory management circuit isfurther configured to issue a first command sequence to select a firstphysical erasing unit from the at least one physical erasing unitavailable for writing and write data corresponding to the first writecommand to at least one first physical programming unit of the firstphysical erasing unit by using a single page programming mode or amulti-page programming mode, when the number of the at least onephysical erasing unit available for writing in the plurality of physicalerasing units is not greater than the first threshold, the memorymanagement circuit is further configured to issue a second commandsequence to select a second physical erasing unit from the at least onephysical erasing unit available for writing and write the datacorresponding to the first write command to at least one second physicalprogramming unit of the second physical erasing unit by only using thesingle page programming mode.
 9. The memory control circuit unit asclaimed in claim 8, wherein the memory management circuit is furtherconfigured to determine whether the number of the at least one physicalerasing unit available for writing in the plurality of physical erasingunits is not greater than a second threshold, and when the number of theat least one physical erasing unit available for writing in theplurality of physical erasing units is not greater than the secondthreshold, the memory management circuit is further configured toperform a valid data merging operation, wherein the second threshold issmaller than the first threshold.
 10. The memory control circuit unit asclaimed in claim 9, wherein in the operation of performing the validdata merging operation, the memory management circuit is furtherconfigured to copy, by using the multi-page programming, a plurality ofvalid data written in the single page programming mode to a plurality ofthird physical programming units of a third physical erasing unit of theplurality of physical erasing units.
 11. The memory control circuit unitas claimed in claim 9, wherein when the rewritable non-volatile memorymodule is abnormally powered off and powered back on, the memorymanagement circuit is further configured to perform the operation ofdetermining whether the number of the at least one physical erasing unitavailable for writing in the plurality of physical erasing units is notgreater than the second threshold.
 12. The memory control circuit unitas claimed in claim 8, wherein in the operation of writing the datacorresponding to the first write command to the at least one secondphysical programming unit of the second physical erasing unit by usingthe single page programming mode, after the rewritable non-volatilememory module is powered off and powered back on, the memory managementcircuit is further configured to copy a plurality of valid data in thesecond physical erasing unit to at least one fourth physical programmingunit of a fourth physical erasing unit of the plurality of physicalerasing units by using the single page programming mode.
 13. The memorycontrol circuit unit as claimed in claim 8, wherein the first thresholdis
 15. 14. The memory control circuit unit as claimed in claim 8,wherein the first physical programming unit is constituted by aplurality of first memory cells and the second physical programming unitis constituted by a plurality of second memory cells. in the single pageprogramming mode, each of the plurality of first memory cellsconstituting the first physical programming unit and each of theplurality of second memory cells constituting the second physicalprogramming unit stores only one bit of data, and in the multi-pageprogramming mode, each of the plurality of first memory cellsconstituting the first physical programming unit stores multiple bits ofdata.
 15. A memory storage device, comprising: a connection interfaceunit configured to couple to a host system; a rewritable non-volatilememory module comprising a plurality of physical erasing units, and eachof the physical erasing units comprising a plurality of physicalprogramming units; and a memory control circuit unit coupled to theconnection interface unit and the rewritable non-volatile memory module,wherein the memory control circuit unit is configured to receive a firstwrite command from the host system, wherein the memory control circuitunit is further configured to determine whether the number of at leastone physical erasing unit available for writing in the plurality ofphysical erasing units is greater than a first threshold, when thenumber of the at least one physical erasing unit available for writingin the plurality of physical erasing units is greater than the firstthreshold, the memory control circuit unit is further configured toissue a first command sequence to select a first physical erasing unitfrom the at least one physical erasing unit available for writing andwrite data corresponding to the first write command to at least onefirst physical programming unit of the first physical erasing unit byusing a single page programming mode or a multi-page programming mode,and when the number of the at least one physical erasing unit availablefor writing in the plurality of physical erasing units is not greaterthan the first threshold, the memory control circuit unit is furtherconfigured to issue a second command sequence to select a secondphysical erasing unit from the at least one physical erasing unitavailable for writing and write the data corresponding to the firstwrite command to at least one second physical programming unit of thesecond physical erasing unit by only using the single page programmingmode.
 16. The memory storage device as claimed in claim 15, wherein thememory control circuit unit is further configured to determine whetherthe number of the at least one physical erasing unit available forwriting in the plurality of physical erasing units is not greater than asecond threshold, and when the number of the at least one physicalerasing unit available for writing in the plurality of physical erasingunits is not greater than the second threshold, the memory controlcircuit unit is further configured to perform a valid data mergingoperation, wherein the second threshold is smaller than the firstthreshold.
 17. The memory storage device as claimed in claim 16, whereinin the operation of performing the valid data merging operation, thememory control circuit unit is further configured to copy, by using themulti-page programming, a plurality of valid data written in the singlepage programming mode to a plurality of third physical programming unitsof a third physical erasing unit of the plurality of physical erasingunits.
 18. The memory storage device as claimed in claim 16, whereinwhen the rewritable non-volatile memory module is abnormally powered offand powered back on, the memory control circuit unit is furtherconfigured to perform the operation of determining whether the number ofthe at least one physical erasing unit available for writing in theplurality of physical erasing units is not greater than the secondthreshold.
 19. The memory storage device as claimed in claim 15, whereinin the operation of writing the data corresponding to the first writecommand to the at least one second physical programming unit of thesecond physical erasing unit by using the single page programming mode,after the rewritable non-volatile memory module is powered off andpowered back on, the memory control circuit unit is further configuredto copy a plurality of valid data in the second physical erasing unit toat least one fourth physical programming unit of a fourth physicalerasing unit of the plurality of physical erasing units by using thesingle page programming mode.
 20. The memory storage device as claimedin claim 15, wherein the first threshold is
 15. 21. The memory storagedevice as claimed in claim 15, wherein the first physical programmingunit is constituted by a plurality of first memory cells and the secondphysical programming unit is constituted by a plurality of second memorycells. in the single page programming mode, each of the plurality offirst memory cells constituting the first physical programming unit andeach of the plurality of second memory cells constituting the secondphysical programming unit stores only one bit of data, and in themulti-page programming mode, each of the plurality of first memory cellsconstituting the first physical programming unit stores multiple bits ofdata.